2002.04.05 Ver. 2.1
MITSUBISHI LSIs
M5M5Y816WG -55HI, -70HI, -85HI
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC# control mode)
tCW
A 0~18
BC1#,BC2#
tsu (A)
tsu (BC1) or
tsu (BC2)
trec (W)
S1#
S2
W#
DQ1~16
(Note5)
(Note5)
(Note7)
(Note5)
(Note6)
tsu (D) th (D)
DATA IN
STABLE
(Note5)
(Note5)
(Note5)
Note 5: Hatching indicates the state is "don't care".
Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low.
Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling
edge of S1# or rising edge of S2, the outputs are maintained in the high impedance state.
Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode.
MITSUBISHI ELECTRIC
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