F8P6LE Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

F8P6LE

8A, 60V, 0.300 Ohm, ESD Rated, Logic Level, P-Channel Power MOSFET

Intersil 

RFD8P06LE, RFD8P06LESM, RFP8P06LE

Typical Performance Curves Unless Otherwise Specified

1.4

VGS = VDS, ID = -250µA

1.2

1.0

0.8

0.6

-80

-40

0

40

80 120 160 200

TJ, JUNCTION TEMPERATURE (oC)

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

-60

VDD =BVDSS

-45

VDD = BVDSS

RL = 7.5Ω

-30

IG(REF) = -0.20mA

0.75 BVDSS 0.75 BVDSS

0.50 BVDSS 0.50 BVDSS

-15

0.25 BVDSS 0.25 BVDSS

VGS = -5V

-5.00

-3.75

-2.50

-1.25

0

IG(REF)

20

IG(ACT)

t, TIME ( µs)

IG(REF)

80

IG(ACT)

0.00

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

125

VDD = -30V, ID = -8A, RL= 3.75Ω

tr

100

75

td(OFF)

50

tf

25

td(ON)

0

0

10

20

30

40

50

RGS, GATE TO SOURCE RESISTANCE (Ω)

FIGURE 13. SWITCHING TIME AS A FUNCTION OF GATE

RESISTANCE

1000

800

600

CISS

VGS = 0V, f = 0.1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

400

COSS

200

CRSS

0

0

-10

-20

-30

-40

-50

-60

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

Test Circuits and Waveforms

VARY tP TO OBTAIN

REQUIRED PEAK IAS

RG

0V

tP

-VGS

VDS

L

DUT

-

VDD

+

IAS

0.01Ω

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT

tAV

0

VDD

IAS

tP

BVDSS

VDS

FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

7-15

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