RF2958 Ver la hoja de datos (PDF) - RF Micro Devices

Número de pieza

componentes Descripción

Fabricante

RF2958

2.4GHz SPREAD-SPECTRUM TRANSCEIVER

RF Micro Devices 

RF2958

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Pkg

Base

Function

IF IN+

IF IN-

VCC IF

R BIAS

VCC RF2

VCC RF1

IF OUT-

IF OUT+

TX VGC

RF OUT

VCC RF3

RF IN

LNA GS

VCC PLL1

PLL REG

MODE1

MODE0

MCLK

SDI

SSB

SCLK

VCC PLL4

DIG REG

VREF

Q BYP

TX Q

I BYP

TX I

VCC BB

RX Q

RX I

RX VGC

GND

Description

Differential input from IF SAW filter. See application schematic for matching circuit.

See pin 1.

Power supply for IF circuitry. Provide 330pF bypass capacitor close to this pin.

Bandgap voltage reference for on-chip biasing. Install a 22.1kΩ,

1% resistor from this pin to ground.

Power supply for TX and RX bias, LO buffers and mixers. Provide 6pF bypass capacitor close to this pin.

See pin 5.

Differential output to IF SAW filter. See application schematic for matching circuit.

See pin 7.

TX analog gain control. Depending on desired operation mode, transmitter gain can be controlled through

this pin or the three-wire digital interface. This pin can also provide a bias voltage to an external PA. See

theory of operation for details.

TX PA driver output.

Power supply for LNA and TX output driver. Power should be connected to this pin through an inductor or a

long 50Ω transmission line RF-shorted with a 6pF capacitor at the other end.

RX input from antenna.

Gain select pin for the internal LNA. High-gain operation is selected when this pin is a logic ‘1’.

Power supply for the PLL RF LO synthesizer. Provide 0.01µF and 6pF bypass capacitors close to this pin.

Internal PLL regulator output. Bypass with 10nF capacitor. Do not connect to VCC or ground.

Controls operational state of the device. See Theory of Operation section for details.

See pin 16.

Reference oscillator for the PLL synthesizer.

Data signal for the synchronous three-wire digital control interface.

Chip select signal for the synchronous three-wire digital control interface.

Clock signal for the synchronous three-wire digital control interface.

Power supply for the PLL IF LO synthesizer. Provide 0.01µF and 330pF bypass capacitors close to this

pin.

Internal digital regulator output. Bypass with 10nF capacitor. Do not connect to VCC or ground.

I/Q DC reference voltage for the baseband processor. This pin should be connected to a high impedance

on the baseband processor.

Baseband differential input signal for the TX quadrature channel. For single-ended applications, bypass to

ground with a 0.01µF capacitor.

Baseband input signal for the TX quadrature channel.

Baseband differential input signal for the TX in-phase channel. For single-ended applications, bypass to

ground with a 0.01µF capacitor.

Baseband input signal for the TX in-phase channel.

Power supply for baseband circuitry. Provide 0.01µF bypass capacitor close to this pin.

Baseband output signal for the RX quadrature channel.

Baseband output signal for the RX in-phase channel.

Analog gain control for the RF IF amplifier.

Device ground. Connect directly to PCB ground plane.

ESD

All pins except pin 12 are provided with electrostatic discharge protection to 3kV using the human body

model.

11-268

Rev A0 050209

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