MTV012A Ver la hoja de datos (PDF) - Myson Century Inc

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MTV012A

8051 Embedded CRT Monitor Controller Mask Version

Myson Century Inc 

MYSON

TECHNOLOGY

MTV012A

STF

P4OUT (w) :

= 1 → Enables STOUT output.

= 0 → Disables STOUT output.

Port 4 data output value.

INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding

interrupt enable bit is set, the 8051 core's INT1 source will be driven by a zero level.

Software MUST clear this register while serving the interrupt routine.

HPRchg= 1 → No action.

= 0 → Clears HSYNC presence change flag.

VPRchg= 1 → No action.

= 0 → Clears VSYNC presence change flag.

HPLchg= 1 → No action.

= 0 → Clears HSYNC polarity change flag.

VPLchg = 1 → No action.

= 0 → Clears VSYNC polarity change flag.

HFchg = 1 → No action.

= 0 → Clears HSYNC frequency change flag.

VFchg = 1 → No action.

= 0 → Clears VSYNC frequency change flag.

INTFLG (r) : Interrupt flag.

HPRchg= 1 → Indicates an HSYNC presence change.

VPRchg= 1 → Indicates a VSYNC presence change.

HPLchg= 1 → Indicates an HSYNC polarity change.

VPLchg = 1 → Indicates a VSYNC polarity change.

HFchg = 1 → Indicates an HSYNC frequency change or counter overflow.

VFchg = 1 → Indicates a VSYNC frequency change or counter overflow.

INTEN (w) :

EHPR

EVPR

EHPL

EVPL

EHF

EVF

Interrupt enabler.

= 1 → Enables HSYNC presence change interrupt.

= 1 → Enables VSYNC presence change interrupt.

= 1 → Enables HSYNC polarity change interrupt.

= 1 → Enables VSYNC polarity change interrupt.

= 1 → Enables HSYNC frequency change / counter overflow interrupt.

= 1 → Enables VSYNC frequency change / counter overflow interrupt.

5. DDC & IIC Interface

5.1 DDC1 Mode

MTV012A enters DDC1 mode after reset. In this mode, VSYNC is used as a data clock when the HSCL

pin remains at high. The data stream taken from an 8-bit FIFO in MTV012A is sent in a 9-bit packet that

includes a null bit (=1) as packet separator. The software program should take care of the FIFO depth.

The FIFO generates a FIFOI interrupt when there are fewer than N (N = 1, 2, 3 or 4 controlled by LS1,

LS0) bytes to be output to the HSDA line. On the other hand, the FIFO sets the FIFOH flag when there

are more than 7 bytes queuing for output. The FIFOI interrupt can be enabled or disabled by S/W. A

simple way to control FIFO is to set {LS1,LS0}={1,0} and enable FIFOI, then load FIFO 4 bytes every

time a FIFOI interrupt occurs. A special control bit "LDFIFO" can reduce S/W effort when EDID data is

saved in EEPROM. If LDFIFO=1, FIFO will be automatically loaded when S/W reads MBUF XFR.

5.2 DDC2B Mode

MTV012A switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once

MTV012A enters DDC2B mode, the host can access the EEPROM using IIC bus protocol as if the

HSDA and HSCL are directly bypassed to ISDA and ISCL pins. MTV012A will return to DDC1 mode if

HSCL is kept high for a 128-VSYNC clock period. However, it will permanently remain in DDC2B mode

if a valid IIC access has been detected on the HSCL/HSDA bus. The DDC2 flag reflects the current DDC

MTV012A Revision 1.1 12/23/1998

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