R4F20223DFD Ver la hoja de datos (PDF) - Renesas Electronics
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R4F20223DFD Datasheet PDF : 992 Pages
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2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................ 55
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) .................................. 55
2.7.8 Memory Indirect—@@aa:8 ............................................................................... 56
2.7.9 Effective Address Calculation ............................................................................ 57
2.8 Processing States ................................................................................................................ 59
2.9 Usage Notes ........................................................................................................................ 61
2.9.1 TAS Instruction .................................................................................................. 61
2.9.2 STM and LDM Instructions................................................................................ 61
2.9.3 Note on Bit Manipulation Instructions................................................................ 61
2.9.4 EEPMOVE Instruction ....................................................................................... 62
Section 3 Exception Handling ............................................................................. 63
3.1 Exception Handling Types and Priority.............................................................................. 63
3.2 Exception Handling Sources and Vector Table .................................................................. 63
3.3 Reset ................................................................................................................................... 64
3.3.1 Reset Sources...................................................................................................... 64
3.3.2 Reset Exception Handling .................................................................................. 67
3.3.3 Interrupts immediately after Reset...................................................................... 68
3.3.4 On-Chip Peripheral Functions after Reset Release............................................. 68
3.4 Trace Exception Handling .................................................................................................. 69
3.5 Interrupt Exception Handling ............................................................................................. 70
3.6 Trap Instruction Exception Handling.................................................................................. 70
3.7 Stack Status after Exception Handling ............................................................................... 71
3.8 Usage Note ......................................................................................................................... 72
Section 4 Interrupt Controller.............................................................................. 73
4.1 Features............................................................................................................................... 73
4.2 Register Descriptions.......................................................................................................... 75
4.2.1 Interrupt Control Register (INTCR) ................................................................... 76
4.2.2 Interrupt Priority Registers A to I (IPRA to IPRI).............................................. 77
4.2.3 IRQ Enable Register (IER) ................................................................................. 79
4.2.4 IRQ Sense Control Register H and L (ISCRH and ISCRL) ............................... 80
4.2.5 IRQ Status Register (ISR)................................................................................... 83
4.2.6 IRQ Noise Canceler Control Register (INCCR)................................................. 84
4.2.7 Interrupt Vector Offset Register (VOFR) ........................................................... 85
4.2.8 Event Link Interrupt Control Status Register (ELCSR) ..................................... 86
4.3 Interrupt Sources................................................................................................................. 87
4.3.1 External Interrupt sources ................................................................................... 87
4.3.2 Internal Interrupts ............................................................................................... 88
4.4 Interrupt Exception Handling Vector Table........................................................................ 89
Rev. 1.00 Oct. 03, 2008 Page x of xxvi
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