QT1080 Ver la hoja de datos (PDF) - Quantum Research Group
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QT1080 Datasheet PDF : 14 Pages
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The 100nF capacitor connected to SS (Figures 1.1 and 1.2)
should be adjusted so that the waveform approximates the
above amplitude, +/-10%, during normal operation in the
target circuit. If this is done, the circuit will give a spectral
modulation of 12-15%.
3.3 Cs Sample Capacitors; Sensitivity
The Cs sample capacitors accumulate the charge from the
key electrodes and determine sensitivity. Higher values of
Cs make the corresponding sensing channel more sensitive.
The values of Cs can differ for each channel, permitting
differences in sensitivity from key to key or to balance
unequal sensitivities. Unequal sensitivities can occur due to
key size and placement differences and stray wiring
capacitances. More stray capacitance on a sense trace will
desensitize the corresponding key; increasing the Cs for that
key will compensate for the loss of sensitivity.
The Cs capacitors can be virtually any plastic film or low to
medium-K ceramic capacitor. The ‘normal’ Cs range is 2.2nF
to 50nF depending on the sensitivity required; larger values
of Cs require better quality to ensure reliable sensing.
Acceptable capacitor types for most uses include PPS film,
polypropylene film, and NP0 and X7R ceramics. Lower
grades than X7R are not advised.
The required values of Cs can be noticeably affected by the
presence and connection of the option resistors (see Section
2.2).
3.4 Power Supply
The power supply can range from 2.8 to 5. 0 volts. If this
fluctuates slowly with temperature, the device will track and
compensate for these changes automatically with only minor
changes in sensitivity. If the supply voltage drifts or shifts
quickly, the drift compensation mechanism will not be able to
keep up, causing sensitivity anomalies or false detections.
The power supply should be locally regulated using a
3-terminal device, to between 2.8V and 5 .0V. If the supply is
shared with another electronic system, care should be taken
to ensure that the supply is free of digital spikes, sags, and
surges which can cause adverse effects.
For proper operation a 0.1µF or greater bypass capacitor
must be used between Vdd and Vss; the bypass capacitor
should be routed with very short tracks to the device’s Vss
and Vdd pins.
3.5 PCB Layout and Construction
Please refer to Quantum application note AN-KD02 for
information related to layout and construction matters.
lQ
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QT1080 R11.03/0905
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