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PSD813F1-A

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

Preliminary

3.0

General

Information

PSD813F1-A

The PSD813F1 series architecture allows In-System Programming of all Memory, PLD

Logic and Device Configuration. The embedded Input and Output Micro⇔Cells enable

efficient implementation of user defined logic functions that require both software and

hardware interaction. The devices eliminate the need for discrete ‘glue’ logic, and allow the

development of entire systems using only a few highly integrated devices.

4.0

PSD813F1

Family

All PSD813F1 devices provide these features: 1 Mbit main Flash Memory, JTAG port,

CPLD, DPLD, power management, and 27 I/O pins. The PSD813F1 also adds 64 bytes of

OTP memory for any use (product serial number, calibration constants, etc.). Once written,

the OTP memory can never be altered.

The following table summarizes the PSD813F1:

Table 1. PSD813F1 Product Matrix

Part #

PSD813F1

Family

Device

No. of Serial ISP

I/O Micro⇔Cells JTAG/ISC

Pins Input/Output Port

Flash

Main Memory

Kbit

(8 Sectors)

Additional

Memory for

Boot and/or Data

(4 Sectors)

SRAM Turbo Supply

Kbit Mode Voltage

PSD813F1 PSD813F1

27

24/16

Yes

1024

256 Kbit EEPROM 16 Yes

5V

PSD813F1V PSD813F1V 27

24/16

Yes

1024

256 Kbit EEPROM 16 Yes

3V

5

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