PSD813F1-A Ver la hoja de datos (PDF) - STMicroelectronics
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PSD813F1-A Datasheet PDF : 120 Pages
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PSD813F1-A
1.0
Introduction
(Cont.)
2
Preliminary
The PSD813F1 family offers two methods to program PSD Flash memory while the PSD is
soldered to a circuit board.
t In-System Programming (ISP) JTAG
An IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire
device (Flash memory, EEPROM, the PLD, and all configuration) to be rapidly
programmed while soldered to the circuit board. This requires no MCU participation,
which means the PSD can be programmed anytime, even while completely blank.
The innovative JTAG interface to flash memories is an industry first, solving key
problems faced by designers and manufacturing houses, such as:
• First time programming – How do I get firmware into the flash the very first time?
JTAG is the answer, program the PSD while blank with no MCU involvement.
• Inventory build-up of pre-programmed devices – How do I maintain an accurate
count of pre-programmed flash memory and PLD devices based on customer
demand? How many and what version? JTAG is the answer, build your hardware
with blank PSDs soldered directly to the board and then custom program just before
they are shipped to customer. No more labels on chips and no more wasted
inventory.
• Expensive sockets – How do I eliminate the need for expensive and unreliable
sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program
first time and subsequent times with JTAG. No need to handle devices and bend the
fragile leads.
t In-Application Programming (IAP)
Two independent memory arrays (Flash and EEPROM) are included so the MCU can
execute code from one memory while erasing and programming the other. Robust
product firmware updates in the field are possible over any communication channel
(CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are
relieved of these problems:
• Simultaneous read and write to flash memory – How can the MCU program the
same memory from which it is executing code? It cannot. The PSD allows the MCU
to operate the two memories concurrently, reading code from one while erasing and
programming the other during IAP.
• Complex memory mapping – I have only a 64K-byte address space to start with.
How can I map these two memories efficiently? A Programmable Decode PLD is the
answer. The concurrent PSD memories can be mapped anywhere in MCU address
space, segment by segment with extremely high address resolution. As an option,
the secondary flash memory can be swapped out of the system memory map when
IAP is complete. A built-in page register breaks the 64K-byte address limit.
• Separate program and data space – How can I write to flash or EEPROM memory
while it resides in “program” space during field firmware updates, my MCU won’t
allow it! The flash PSD provides means to “reclassify” flash or EEPROM memory as
“data” space during IAP, then back to “program” space when complete.
PSDsoft — ST’s software development tool — now has the ability to generate
ANSI-C compliant code for use with your target MCU. The code generated allows you to
manipulate the non-volatile memory (NVM) within the PSD. Code examples are also
provided for:
• Flash ISP via the UART of the host MCU
• Memory paging to execute code across several PSD memory pages
• Loading, reading, and manipulation of PSD Micro⇔Cells by the MCU
The PSD813F1 is available in a 52-pin PLCC package and a 64-pin plastic Thin Quad
Flatpack (TQFP) package.
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