PSD813F1-A Ver la hoja de datos (PDF) - STMicroelectronics
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PSD813F1-A Datasheet PDF : 120 Pages
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PSD813F1-A
8.0
PSD813F1
Register
Description
and Address
Offset
Preliminary
Table 7 shows the offset addresses to the PSD813F1 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD813F1 registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
Table 7. Register Address Offset
Register Name Port A Port B Port C Port D Other*
Description
Data In
00 01 10 11
Reads Port pin as input,
MCU I/O input mode
Control
02 03
Selects mode between
MCU I/O or Address Out
Data Out
04 05 12 13
Stores data for output
to Port pins, MCU I/O
output mode
Direction
06 07 14 15
Configures Port pin as
input or output
Drive Select
08 09 16 17
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Input Micro⇔Cell 0A 0B 18
Reads Input Micro⇔Cells
Enable Out
0C 0D 1A 1B
Reads the status of the
output enable to the I/O
Port driver
Output
Micro⇔Cells AB
20
20
Read – reads output of
Micro⇔Cells AB
Write – loads Micro⇔cell
Flip-Flops
Output
Micro⇔Cells BC
21 21
Read – reads output of
Micro⇔Cells BC
Write – loads Micro⇔cell
Flip-Flops
Mask
Micro⇔Cells AB
22
22
Blocks writing to the
Output Micro⇔Cells AB
Mask
Micro⇔Cells BC
23 23
Blocks writing to the
Output Micro⇔Cells BC
Flash Protection
C0
Read only – Flash Sector
Protection
PSD/EE
Protection
Read only – PSD Security
C2
and EEPROM Sector
Protection
JTAG Enable
C7 Enables JTAG Port
PMMR0
B0
Power Management
Register 0
PMMR2
B4
Power Management
Register 2
Page
E0 Page Register
Places PSD memory
VM
E2
areas in Program and/or
Data space on an
individual basis.
*Other registers that are not part of the I/O ports.
14
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