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PSD813F1-A

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

Preliminary

Table 5.

PSD813F1

Pin

Descriptions

(cont.)

PSD813F1-A

Pin Name Pin* Type

CNTL2

49 I

Reset

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

48 I

29 I/O

28

27

25

24

23

22

21

PB0

7 I/O

PB1

6

PB2

5

PB3

4

PB4

3

PB5

2

PB6

52

PB7

51

PC0

20 I/O

PC1

19 I/O

Description

This port can be used to input the PSEN (Program Select

Enable) signal from any MCU that uses this signal for code

exclusively. If your MCU does not output a Program Select

Enable signal, this port can be used as a generic input. This

port is connected to the PLDs.

Active low reset input. Resets I/O Ports, PLD Micro⇔Cells

and some of the configuration registers. Must be active at

power up.

These pins make up Port A. These port pins are configurable

and can have the following functions:

1. MCU I/O — write to or read from a standard output or

input port.

2. CPLD Micro⇔Cell (McellAB0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 6).

5. Address inputs. For example, PA0-3 could be used for

A[0:3] when using an 80C51XA in burst mode.

6. As the data bus inputs D[0:7] for non-multiplexed

address/data bus MCUs.

7. D0/A16-D3/A19 in M37702M2 mode.

8. Peripheral I/O mode.

Note: PA0-3 can only output CMOS signals with an option

for high slew rate. However, PA4-7 can be configured as

CMOS or Open Drain Outputs.

These pins make up Port B. These port pins are configurable

and can have the following functions:

1. MCU I/O — write to or read from a standard output or

input port.

2. CPLD Micro⇔Cell (McellAB0-7 or McellBC0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 6).

Note: PB0-3 can only output CMOS signals with an option

for high slew rate. However, PB4-7 can be configured as

CMOS or Open Drain Outputs.

PC0 pin of Port C. This port pin can be configured to have

the following functions:

1. MCU I/O — write to or read from a standard output or

input port.

2. CPLD Micro⇔Cell (McellBC0) output.

3. Input to the PLDs.

4. TMS Input** for the JTAG Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1 pin of Port C. This port pin can be configured to have

the following functions:

1. MCU I/O — write to or read from a standard output or

input port.

2. CPLD Micro⇔Cell (McellBC1) output.

3. Input to the PLDs.

4. TCK Input** for the JTAG Interface.

This pin can be configured as a CMOS or Open Drain output.

11

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