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M28F008

8-Mbit (1Mbit x 8) flash memory

Intel 

M28F008

Erase Setup Erase Confirm

Commands

Erase is executed one block at a time initiated by a

two-cycle command sequence An Erase Setup

command (20H) is first written to the Command User

Interface followed by the Erase Confirm command

(D0H) These commands require both appropriate

sequencing and an address within the block to be

erased to FFH Block preconditioning erase and

verify are all handled internally by the Write State

Machine invisible to the system After the two-com-

mand erase sequence is written to it the M28F008

automatically outputs Status Register data when

read (see Figure 6 Block Erase Flowchart) The

CPU can detect the completion of the erase event

by analyzing the output of the RY BY pin or the

WSM Status bit of the Status Register

When erase is completed the Erase Status bit

should be checked If erase error is detected the

Status Register should be cleared The Command

User Interface remains in Read Status Register

mode until further commands are issued to it

This two-step sequence of set-up followed by execu-

tion ensures that memory contents are not acciden-

tally erased Also reliable block erasure can only

occur when VPP e VPPH In the absence of this high

voltage memory contents are protected against era-

sure If block erase is attempted while VPP e VPPL

the VPP Status bit will be set to ‘‘1’’ Erase attempts

while VPPL k VPP k VPPH produce spurious results

and should not be attempted

Erase Suspend Erase Resume

Commands

The Erase Suspend command allows block erase

interruption in order to read data from another block

of memory Once the erase process starts writing

the Erase Suspend command (B0H) to the Com-

mand User Interface requests that the WSM sus-

pend the erase sequence at a predetermined point

in the erase algorithm The M28F008 continues to

output Status Register data when read after the

Erase Suspend command is written to it Polling the

WSM status and Erase Suspend status bits will de-

termine when the erase operation has been sus-

pended (both will be set to ‘‘1’’) RY BY will also

transition to VOH

At this point a Read Array command can be written

to the Command User Interface to read data from

blocks other than that which is suspended The only

other valid commands at this time are Read Status

Register (70H) and Erase Resume (D0H) at which

time the WSM will continue with the erase process

The Erase Suspend status and WSM status bits of

the Status Register will be automatically cleared and

RY BY will return to VOL After the Erase Resume

command is written to it the M28F008 automatically

outputs Status Register data when read (see Figure

7 Erase Suspend Resume Flowchart) VPP must re-

main at VPPH while the M28F008 is in Erase Sus-

pend

Byte Write Setup Write Commands

Byte write is executed by a two-command sequence

The Byte Write Setup command (40H) is written to

the Command User Interface followed by a second

write specifying the address and data (latched on

the rising edge of WE) to be written The WSM then

takes over controlling the byte write and write verify

algorithms internally After the two-command byte

write sequence is written to it the M28F008 auto-

matically outputs Status Register data when read

(see Figure 5 Byte Write Flowchart) The CPU can

detect the completion of the byte write event by ana-

lyzing the output of the RY BY pin or the WSM

status bit of the Status Register Only the Read

Status Register command is valid while byte write is

active

When byte write is complete the Byte Write status

bit should be checked If byte write error is detected

the Status Register should be cleared The internal

WSM verify only detects errors for ‘‘1’’s that do not

successfully write to ‘‘0’’s The Command User In-

terface remains in Read Status Register mode until

further commands are issued to it If byte write is

attempted while VPP e VPPL the VPP Status bit will

be set to ‘‘1’’ Byte write attempts while

VPPL k VPP k VPPH

produce spurious results and should not be attempt-

ed

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