SBSLITE™ Telecom Standard Product Data Sheet
Preliminary
• Uses 8B/10B-based line coding protocol on the serial links to provide transition density
guarantee and DC balance and to offer a greater control character vocabulary than the
standard 8B/10B protocol.
• Provides optional pseudo-random bit sequence (PRBS) generation for each outgoing LVDS
serial data link for off-line link verification. PRBS can be inserted with STS-1 granularity.
• Provides PRBS detection for each incoming LVDS serial link for off-line link verification.
PRBS is verified with STS-1 granularity.
• Provides pins to coordinate updating of the connection map of the memory switch blocks in
the local device, peer SBSLITE devices and companion NSE switch device.
• Can communicate with the NSE switch device over an in-band communications channel in
the LVDS links. This channel includes mechanisms for central control and configuration.
• Derives all internal timing from a single 77.76 MHz system clock to a system frame pulse.
• Implemented in 1.8 V/3.3 V 0.18 µm CMOS and packaged in a 160 ball 15 mm x 15 mm
PBGA.
• Consumes low power at 1.4 W.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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Document ID: PMC-2010883, Issue 2