PM5313 Ver la hoja de datos (PDF) - PMC-Sierra

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Fabricante

PM5313

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PMC-Sierra 

PRODUCTION

DATASHEET

PMC-1981162

ISSUE 6

PMC-Sierra, Inc.

PM5313 SPECTRA-622

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

Issue No. Issue Date

Issue 6 Sept 2000

Issue 5 May 2000

Details of Change

• Remove support of in-band G1 reporting on

DROP bus

• Improve RAD Timing diagram (Fig 60)

• Pointer justification not generated in PAIS on

DROP bus

• Specify that the jitter tolerance is according to the

1995 Bellcore spec.

• Remove the K1 and K2 bytes from the RAD.

• Specify that a RESET_PATH command will also

clear the performing monitor counters of the

section/line TSBs.Update AC and DC

Characeristic sections according to its final

report..

• V1 pulse is always outputted on the DROP bus

when the RTAL FIFO is bypassed

• Add the RESET sequence to enable the TX line

interface and the OUTDATA bit in the CRSI.

• Specify TFPO timing in serial mode

• CRU and CSU will track REFCLK while in ROOL

• Describe RX and TX bypass mode limitations

• SDLE and RBYP mode can not be set at the

same time.

• Fix number of bits before a DOOL is declared

from 80 to 96.

• Bit 7 of register 0090H is now X vs 0.

• Write to the PMON counter registers will also

trigger a count transfer.

• SS bits are always 00 when the DPGM is in

autonomous mode.

• Add WANS programming section

• Update the RAD and TFPI timing diagrams.

• Update rev of CRU, GPGM and TTOC.

• Update the methodology Tools table.

• Added STM1-CONCAT register bits in RPPS and

TPPS configuration.

• Extend the timing for output pins RSUC, RSOW,

ROH and TDO.

PROPRIETARY AND CONFIDENTIAL

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