P130-69 Ver la hoja de datos (PDF) - PhaseLink Corporation

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Fabricante

P130-69

High Speed Translator Buffers: Single ended to PECL or LVDS

PhaseLink Corporation 

PLL130-68/-69

High Speed Translator Buffers: Single ended to PECL or LVDS

PIN DESCRIPTION

Name

NC

REFIN

OECTRL

GND

OESEL

Q_BAR

Q

VDD

Q

Q_BAR

Pin number

1, 3, 4, 6,

8, 12, 14

2

5

7

9

10

11

13

15

16

Type

-

I

I

P

I

O

O

P

O

O

Description

No connection.

Reference input signal. The frequency of this signal will be reproduced

at the output (after translation to PECL or LVDS level).

Output enable input (See OE Logic Table on page 1).

Ground connector.

Output enable logic selector (See OE Logic Table on page 1).

Complementary output. PECL_bar on PLL130-68, LVDS_bar on

PLL130-69.

True output. PECL on PLL130-68, LVDS on PLL130-69.

3.3V Power supply.

Additional true output. PECL on PLL130-68, LVDS on PLL130-69. This

output is the same as pin 11.

Additional complementary output. PECL_bar on PLL130-68, LVDS_bar

on PLL130-69. This output is the same as pin 10.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

Input Voltage, dc

Output Voltage, dc

Storage Temperature

Ambient Operating Temperature*

Junction Temperature

Lead Temperature (soldering, 10s)

ESD Protection, Human Body Model

VDD

4.6

V

VI

-0.5

VDD+0.5

V

VO

-0.5

VDD+0.5

V

TS

-65

150

°C

TA

-40

85

°C

TJ

125

°C

260

°C

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-

ditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

2. General Electrical Specifications

PARAMETERS

Supply Current

(both outputs loaded)

Operating Voltage

Output Clock Duty Cycle

Short Circuit Current

SYMBOL

CONDITIONS

Fout = 156.25MHz, PECL

IDD

Fout = 156.25MHz, LVDS

VDD

@ Vdd – 1.3V (PECL)

@ 1.25V (LVDS)

MIN. TYP. MAX.

45

48

51

22

25

28

2.97

3.63

Same as input

Same as input

±50

UNITS

mA

V

%

mA

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 2

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