PLL102-109XM Ver la hoja de datos (PDF) - PhaseLink Corporation

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PLL102-109XM

Programmable DDR Zero Delay Clock Driver

PhaseLink Corporation 

Preliminary PLL102-109

Programmable DDR Zero Delay Clock Driver

8. Byte 11: Buffer Drive Strength Control Register

Bit

Name

Default

Description

Bit 7

-

1

Reserved.

Bit 6

-

1

Reserved.

Bit 5

-

1

Reserved.

Bit 4

-

1

Reserved.

Bit 3

-

1

Reserved.

Bit 2

Bit <2>

Bit 1

FBOUTT

Strength

Bit <1>

Bit 0

Bit <0>

0

1

These three bits will program drive strength for FBOUTT output

clock (see Table 3).

1

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 02/26/03 Page 7

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