PLL102-108XM Ver la hoja de datos (PDF) - PhaseLink Corporation
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PLL102-108XM Datasheet PDF : 10 Pages
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PLL102-108
Programmable DDR Zero Delay Clock Driver
3. Recommended Operating Conditions
PARAMETERS
Output supply voltage
Analog Supply voltage
High level input voltage
Low level input voltage
Operating free-air temperature
SYMBOL
VCC
ACC
VIH
VIL
TA
MIN.
2.3
2.3
0.7 x VCC
0
TYP.
2.5
2.5
MAX.
2.7
2.7
0.3 x VCC
70
UNITS
V
V
V
V
°C
4. Timing requirements
SYMBOL
FCLK
DIN
TS
PARAMETERS
Input clock frequency
Input clock duty cycle
Stabilization time after power up
MIN.
MAX.
UNITS
66
266
MHz
40
60
%
0.1
ms
5. Switching Characteristics
PARAMETERS
Low to high level propagation
delay time
High to low level propagation
delay time
SYMBOL
TPLH
TPHL
Jitter (peak to peak)
Tp-p
Jitter (cycle to cycle)
Phase error
Output to output skew
Pulse skew
Duty Cycle
Rise time, Fall time
Tcyc-cyc
t(phase error)
Toskew
Tpskew
DT
tr, tf
CONDITIONS
CLK_INT to any output
CLK_INT to any output
66MHz
100/133/200/266MHz
66MHz
100/133/200/266MHz
All differential input and output
terminals are terminated with
120Ω/16pF
66MHz to 100MHz
101MHz to 266MHz
Load = 120Ω/16pF
MIN.
-150
49.5
49
650
TYP.
0
0
800
MAX. UNITS
ns
120
75
ps
110
65
ps
150
100
ps
100
50.5
51
%
950
ps
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/29/02 Page 9
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