HI1171 Ver la hoja de datos (PDF) - Intersil

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HI1171

8-Bit, 40 MSPS, High Speed D/A Converter

Intersil 

HI1171

Pin Descriptions (Continued)

24 PIN

SOIC

PIN

NAME

PIN DESCRIPTION

17

18, 19, 22

20

21

23, 24

VG

AVDD

IOUT1

IOUT2

DVDD

Voltage Ground, connect a 0.1µF capacitor to AVDD.

Analog Supply 4.75V to 7V.

Current Output Pin.

Current Output pin used for a virtual ground connection. Usually connected to AVSS.

Digital Supply 4.75V to 7V.

Detailed Description

The HI1171 is an 8-bit, current out D/A converter. The DAC

can convert at 40MHz and run on a single +5V supply. The

architecture is an encoded, switched current cell

arrangement.

Voltage Output Mode

The output current of the HI1171 can be converted into a volt-

age by connecting an external resistor to IOUT1. To calculate

the output resistor use the following equation:

As the values of both ROUT and RREF increase, power

consumption is decreased, but glitch energy and output

settling time is increased.

Clock Phase Relationship

The internal latch is closed when the clock line is high. The

latch can be cleared by the BLNK line. When BLNK is set

(HIGH) the contents of the internal data latch will be cleared.

When BLNK is low data is updated by the CLK.

ROUT = VFS /IFS,

where VFS can range from +0.5V to +2.0V and IFS can

range from 0mA to 15mA.

In setting the output current the IREF pin should have a resistor

connected to it that is 16 times greater than the output resistor:

RREF = 16 x ROUT

Noise Reduction

To reduce power supply noise separate analog and digital

power supplies should be used with 0.1µF ceramic capaci-

tors placed as close to the body of the HI1171 as possible.

The analog (AVSS) and digital (DVSS) ground returns should

be connected together back at the power supply to ensure

proper operation from power up.

Test Circuits

8-BIT

COUNTER

WITH LATCH

CLK

40MHz

SQUARE WAVE

(LSB) D0

1

2

D7

8

BLK

9

0.1µF

11

VB

12

CLK

IO

20

VG

17

0.1µF

VREF

16

2V

IREF

15

AVDD

OSCILLOSCOPE

200Ω

1kΩ

AVSS

3.3kΩ

FIGURE 5. MAXIMUM CONVERSION SPEED TEST CIRCUIT

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

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