HI1176 Ver la hoja de datos (PDF) - Intersil
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HI1176 Datasheet PDF : 12 Pages
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HI1176
TABLE 1. A/D OUTPUT CODE
INPUT SIGNAL
VOLTAGE
STEP
MSB
DIGITAL OUTPUT CODE
LSB
VRT
255
•
•
•
•
•
•
•
128
•
127
•
•
•
•
•
•
VRB
0
Detailed Description
1
1
1
1
1
1
1
1
•
•
•
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
•
•
•
0
0
0
0
0
0
0
0
The HI1176 is a 2-step A/D converter featuring a 4-bit upper
comparator group and two lower comparator groups of 4 bits
each. The reference voltage can obtained from the onboard
bias generator or be supplied externally. This IC uses an off-
set canceling type comparator that operates synchronously
with an external clock. The operating modes of the part are
input sampling/autozero (S), hold (H), and compare (C).
The operation of the part is illustrated in Figure 2. A reference
voltage that is between VRT-VRB is constantly applied to the
upper 4-bit comparator group. VI(1) is sampled with the falling
edge of the first clock by the upper comparator block. The
lower block A also samples VI(1) on the same edge. The
upper comparator block finalizes comparison data MD(1) with
the rising edge of the first clock. Simultaneously the reference
supply generates a reference voltage RV(1) that corresponds
to the upper results and applies it to the lower comparator
block A. The lower comparator block finalizes comparison
data LD(1) with the rising edge of the second clock. MD(1)
and LD(1) are combined and output as OUT(1) with the rising
edge of the third clock. There is a 2.5 cycle clock delay from
the analog input sampling point to the corresponding digital
output data. Notice how the lower comparator blocks A and B
alternate generating the lower data in order to increase the
overall A/D sampling rate.
Power, Grounding, and Decoupling
To reduce noise effects, separate the analog and digital
grounds.
Bypass both the digital and analog VDD pins to their respec-
tive grounds with a ceramic 0.1µF capacitor close to the pin.
Analog Input
The input capacitance is small when compared with other
flash type A/D converters. However, it is necessary to drive
the input with an amplifier with sufficient bandwidth and drive
capability. In order to prevent parasitic oscillation, it may be
necessary to insert a resistor between the output of the
amplifier and the A/D input.
Reference Input
The range of the A/D is set by the voltage between VRT and
VRB. The internal bias generator will set VRTS to 2.5V and
VRBS to 0.5V. These can be used as the part reference by
shorting VRT and VRTS and VRB to VRBS. The analog input
range of the A/D will now be from 0.5V to 2.5V. If a VRB below
+0.5V is used the linearity of the part will be degraded.
Bypass VRT and VRB to analog ground with a 0.1µF
capacitor.
Clamp Operation
The HI1176 provides a clamp option that allows the user to
clamp a portion of the analog input to a voltage set by the
VREF pin. The clamp function is enabled by bringing CLE
low. An internal monostable multivibrator is provided that
can be used to generate the clamp pulses. The monostable
pulse width is determined by the external R and C connected
to the PW pin. The trigger to the monostable is applied on
the SYNC pin. The edge that triggers the monostable is
determined by the SEL pin. When SEL is low the falling edge
will trigger the monostable and when SEL is high the rising
edge will trigger the monostable. Figure 6 shows the HI1176
configured for this mode of operation. The clamp pulse is
latched by the ADC sampling clock. This is not necessary to
the operation of the clamp function but if this is not done then
a slight beat might be generated as vertical sag according to
the relation between the sampling frequency and the clamp
frequency.
The HI1176 can also be configured to operate with an exter-
nal clamp pulse. In this case a negative going pulse is input
to the PW pin. VIN will now be clamped during the low period
of the clamp pulse to the voltage on the VREF pin. Figure 7
shows the HI1176 configured for this mode of operation.
Figure 1 illustrates the operation of HI1176 when the clamp
function is not used.
9
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