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MC14014BFL1

8-Bit Static Shift Register

ON Semiconductor 

MC14014B, MC14021B

8-Bit Static Shift Register

The MC14014B and MC14021B 8–bit static shift registers are

constructed with MOS P–channel and N–channel enhancement mode

devices in a single monolithic structure. These shift registers find

primary use in parallel–to–serial data conversion, synchronous and

asynchronous parallel input, serial output data queueing; and other

general purpose register applications requiring low power and/or high

noise immunity.

• Synchronous Parallel Input/Serial Output (MC14014B)

• Asynchronous Parallel Input/Serial Output (MC14021B)

• Synchronous Serial Input/Serial Output

• Full Static Operation

• “Q” Outputs from Sixth, Seventh, and Eighth Stages

• Double Diode Input Protection

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• MC14014B Pin–for–Pin Replacement for CD4014B

• MC14021B Pin–for–Pin Replacement for CD4021B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage Range

– 0.5 to +18.0

V

Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5

V

(DC or Transient)

Iin, Iout

Input or Output Current

(DC or Transient) per Pin

± 10

mA

PD

Power Dissipation,

per Package (Note 3.)

500

mW

TA

Ambient Temperature Range

Tstg

Storage Temperature Range

TL

Lead Temperature

(8–Second Soldering)

– 55 to +125

°C

– 65 to +150

°C

260

°C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

v v high–impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS (Vin or Vout) VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either VSS or VDD). Unused outputs must be left open.

http://onsemi.com

PDIP–16

P SUFFIX

CASE 648

MARKING

DIAGRAMS

16

MC140XXBCP

AWLYYWW

1

SOIC–16

D SUFFIX

CASE 751B

16

140XXB

AWLYWW

1

SOEIAJ–16

F SUFFIX

CASE 966

16

MC140XXB

AWLYWW

1

XX

= Specific Device Code

A

= Assembly Location

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

ORDERING INFORMATION

Device

Package

Shipping

MC14014BCP

PDIP–16

2000/Box

MC14014BD

SOIC–16

48/Rail

MC14014BDR2 SOIC–16 2500/Tape & Reel

MC14014BF

SOEIAJ–16 See Note 1.

MC14014BFEL SOEIAJ–16 See Note 1.

MC14021BCP

PDIP–16

2000/Box

MC14021BD

SOIC–16

48/Rail

MC14021BDR2 SOIC–16 2500/Tape & Reel

MC14021BF

SOEIAJ–16 See Note 1.

MC14021BFEL SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

© Semiconductor Components Industries, LLC, 2000

1

March, 2000 – Rev. 3

Publication Order Number:

MC14014B/D

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