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PG12864LRU-ORA-H-S0 Ver la hoja de datos (PDF) - Powertip Technology

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PG12864LRU-ORA-H-S0
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PG12864LRU-ORA-H-S0 Datasheet PDF : 32 Pages
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NO.PG12864LRU-ORA-H Rev:0
RE RS D7 D6 D5 D4
D3
D2
D1
D0
0
1
1
0
0
1 REV NLIN SWAP REF
(At the time of reset: (REV, NLIN, SWAP, REF)=0H, read address: 9H)
Various control of display is set up.
(I) REF Command
When MPU accesses to the Graphic Display RAM, the relationship between X address and write data is
normalized or reversed.
Therefore, the order of segment driver output can be reversed by register setting, lessening the limitation of
IC location in assembling into the LCD panel.
ACCESS FROM MPU
REF
X ADDRESS
D7~D0
0
NH
D0(LSB)
D7(MSB)
1
NH
D0(LSB)
D7(MSB)
INTERNAL ACCESS
X ADDRESS
NH
0FH-NH
D7-D0
(LSB)
(MSB)
(MSB)
(LSB)
DDRRESPONDING
SEG OUTPUT
SEG(8*NH) Output
SEG(8*NH+7) Output
SEG(8*(0F-NH)+7) Output
SEG(8*(0F-NH)) Output
When using this command. Output of Segment Display Circuits are set as below.
However the order of D0->D7 are not changed.
ACCESS FROM MPU
REF
X ADDRESS D7~D0
INTERNAL ACCESS
X ADDRESS D7-D0
DDRRESPONDING
SEG OUTPUT
0
00H
D0(LSB)
D7(MSB)
00H
D0(LSB)
D7(MSB)
D7->D0
SEGS0->SEGS7
0
01H
D0(LSB)
D3(MSB)
01H
D0(LSB)
D3(MSB)
D0~D3
SEGS8->SEGS11
1
0FH
D0(LSB)
D7(MSB)
00H
D0(LSB)
D7(MSB)
D0->D7
SEGS0->SEGS7
1
H0E
D0(LSB)
D3(MSB)
01H
D0(LSB)
D3(MSB)
D0->D3
SEGS8->SEGS11
When REF=”1”,please set X address of Segment Display Circuits like below.
00H->0FH
01H->0EH
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