PG12864LRU-ORA-H-S0 Ver la hoja de datos (PDF) - Powertip Technology
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PG12864LRU-ORA-H-S0 Datasheet PDF : 32 Pages
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NO.PG12864LRU-ORA-H Rev:0
2-4.4 Y Address Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
0 AY3 AY2 AY1 AY0
(At the time of reset AX3~AX0 = 0H, read address : 2H)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
1
1 ※ AY6 AY5 AY4
※ mark shows “Don’t care”
(At the time of reset:AY6~AY4=0H, read address:3H
Addresses of Display RAM’s Y direction are set. In data setting, lower place and upper place are divided
with 4 bit and 3 bit respectively.
When data set, lower place must be set first and upper place must be set second.
The values of AY6 to AY0 are usable up to 00H-42H, but 43H-FFH are inhibited.
The addresses of 40H to 42H are for the Segment Display RAM.
2-4.5 Display Starting Line Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0 LY3 LY2 LY1 LY0
(At the time of reset AX3~AX0 = 0H, read address: 4H)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1 ※ ※ LA5 LA4
※ mark shows “Don’t care” (At the time of reset :LA4,LA5 = 0H, read address: 5H)
The display line address is required to designate, and the designated address become the display
line of COM0.
The display of LCD panel is indicated in he increment direction of the designated display starting address to
the line address.
LA5 LA4 LA3 LA2 LA1 LA0
0
0
0
0
0
0
0
0
0
0
0
1
LINE ADDRESS
0
1
1
1
1
1
1
1
63
POWERTIP TECHNOLOGY CORPORATION
DISPLAY DEVICES FOR BETTER ELECTRONIC DESIGN
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