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PEB20324

Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X

Infineon Technologies 

PEB 20324

PEF 20324

Introduction

• Bit Processor Functions (adjustable for each channel)

– HDLC Protocol

– Automatic flag detection

– Shared opening and closing flag

– Detection of interframe-time-fill change, generation of

interframe-time-fill ‘1’s or flags

– Zero bit insertion

– Flag stuffing and flag adjustment for rate adaption

– CRC generation and checking (16 or 32 bits)

– Transparent CRC option per channel and/or per message

– Error detection (abort, long frame, CRC error, 2 categories

of short frames, non-octet frame content)

– ABORT/IDLE flag generation

– V.110/X.30 Protocol

– Automatic synchronization in receive direction, automatic generation of

the synchronization pattern in transmit direction

– E/S/X bits freely programmable in transmit direction, may be changed

during transmission; changes monitored and reported in receive direction

– Generation/detection of loss of synchronism

– Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s

– Transparent Mode A

– Slot synchronous transparent transmission/reception without frame structure

– Flag generation, flag stuffing, flag extraction, flag generation

in the abort case with programmable flag

– Synchronized data transfer for fractional T1/PRI channels

– Transparent Mode B

– Transparent transmission/reception in frames delimited by 00H flags

– Shared opening and closing flag

– Flag stuffing, flag detection, flag generation in the abort case

– Error detection (non octet frame content, short frame, long frame)

– Transparent Mode R

– Transparent transmission/reception with GSM 08.60 frame structure

– Automatic 0000H flag generation/detection

– Support of 40, 391/2, 401/2 octet frames

– Error detection (non octet frame contents, short frame, long frame)

– Protocol Independent

– Channel inversion (data, flags, IDLE code)

– Format conventions as in CCITT Q.921 § 2.8

– Data over- and underflow detected

Hardware Reference Manual

9

04.99

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