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PEB2035 Ver la hoja de datos (PDF) - Siemens AG

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PEB2035 Datasheet PDF : 134 Pages
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Advanced CMOS Frame Aligner (ACFA)
PEB 2035
CMOS IC
1 Features
Serial Interface to Line Interface Unit
q Frame alignment/synthesis for 2048 kbit/s (CEPT,
PCM 30) and 1544 kbit/s (T1, PCM 24)
q Meets newest CCITT Rec’s (Blue Book), FTZ Rec’s and
AT&T technical advisories (DMI, August 1986)
q Programmable formats for
PCM 30: Doubleframe, CRC Multiframe
PCM 24: 4-Frame Multiframe (F4), 12-Frame Multiframe
(F12, D3/4), Extended Superframe (ESF), Remote Switch
Mode (F72)
q Selectable conditions for loss of sync
q Selectable line codes (HDB3, B8ZS, AMI with ZCS)
q Unipolar NRZ for interfacing fibre optical transmission
routes
q Error checking via CRC4 or CRC6 procedures
q Insertion and extraction of alarms and facility signaling
q IDLE code insertion for selectable channels
P-LCC-44
Serial Interface to System Internal Highway
P-DIP-40
q System clock frequency of either 4096 kHz or 8192 kHz
q Selectable 2048/4096 kbit/s system internal highway with programmable receive/transmit shifts
q Two-frame deep elastic receive memory for receive route clock wander and jitter compensation
(can be reduced to one-frame length for PCM 30 master-slave applications)
q One frame elastic transmit memory (PCM 24 mode only) for transmit route clock wander and
jitter compensation
q Two different time-slot assignment procedures in PCM 24 mode
q Support for different signaling schemes
q Channel loop back capabilities
q Channel parity error monitoring
q Clear channel capabilities in PCM 24 mode
Type
PEB 2035-N
PEB 2035-P
Version
V4.1
V4.1
Ordering Code
Q67100-H6289
Q67100-H6290
Package
P-LCC-44 (SMD)
P-DIP-40
Semiconductor Group
4
01.94

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