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PEB2035-N

Advanced CMOS Frame Aligner ACFA

Siemens AG 

PEB 2035

1.3 Pin Definitions and Functions (cont’d)

P-LCC

Pin No.

18

19

20

21

P-DIP Symbol

Pin No.

16

A0

17

A1

18

A2

19

A3

22

20

RDQ

25

21

WRQ

26

22

CEQ

27

23

COS

28

24

SCLK

29

25

RRCLK

Input (I)

Output (O)

I

I

I

I

I

I

I

I

I

I

Function

Address Bus

These inputs interface with four lines of the

system’s address bus to select one of the internal

registers. Write access to address ’0E’ and ’0F’ is

not allowed.

Read Enable (active low)

This signal indicates a read operation. If both CEQ

and RDQ are active, status information of the

registers selected via A0 … A3 will be read from

the ACFA. If access to the internal signaling

stacks is enabled by setting bit XC0.ISIG, the data

from the stack: RSIG may be read when ACKNLQ

and RDQ are active.

Write Enable (active low)

This signal indicates a write operation. If both CEQ

and WRQ are active control information may be

written to the registers selected via A0 … A3. If

access to the internal signaling stacks is enabled

by setting bit XC0.ISIG data may be written to the

stack XSIG when ACKNLQ and WRQ are active.

Chip Enable (active low)

A low signal enables normal read/write access to

the internal registers.

Carrier Out of Service

A high signal at this input enables transmission of

AIS via outputs XDOP, XDOM, and XOID without

any framing structure.

System Clock

Working clock for the ACFA with a frequency of

4096 kHz or 8192 kHz (selected by bit MODE.

SCLK)

Receive Route Clock

Extracted from the incoming data pulses by the

line interface unit (e.g. IPAT, PEB 2235/PEB

2236).

Clock frequency: 2048 kHz [PCM 30]

1544 kHz [PCM 24]

Semiconductor Group

13

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