HT48C06 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT48C06 Datasheet PDF : 38 Pages
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HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC) will be set. When the interrupt is enabled, the
stack is not full and the external interrupt is active, a sub-
routine call to location 04H will occur. The interrupt re-
quest flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the ²RETI²
instruction is executed or the EMI bit and the related in-
terrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a External Interrupt
1
04H
b Timer/Event Counter Overflow 2
08H
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), enable timer/event
counter bit (ETI), enable external interrupt bit (EEI) and
enable master interrupt bit (EMI) constitute an interrupt
control register (INTC) which is located at 0BH in the
data memory. EMI, EEI, ETI are used to control the en-
abling/disabling of interrupts. These bits prevent the re-
quested interrupt from being serviced. Once the
interrupt request flags (TF, EIF) are set, they will remain
in the INTC register until the interrupts are serviced or
cleared by a software instruction.
Labels
C
AC
Z
OV
PDF
TO
¾
¾
Bits
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not take
0 place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by exe-
cuting the ²HALT² instruction.
5
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set
by a WDT time-out.
6 Unused bit, read as ²0²
7 Unused bit, read as ²0²
Status Register
Register
INTC
(0BH)
Bit No.
0
1
2
3
4
5
6
7
Label
EMI
EEI
ETI
¾
EIF
TF
¾
¾
Function
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the external interrupt (1= enabled; 0= disabled)
Controls the timer/event counter interrupt (1= enabled; 0= disabled)
Unused bit, read as ²0²
External interrupt request flag (1= active; 0= inactive)
Internal timer/event counter request flag (1= active; 0= inactive)
Unused bit, read as ²0²
Unused bit, read as ²0²
INTC Register
Rev. 1.10
9
June 9, 2004
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