PCK2002DGG Ver la hoja de datos (PDF) - Philips Electronics
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PCK2002DGG Datasheet PDF : 12 Pages
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Philips Semiconductors
0–300 MHz I2C 1:18 clock buffer
Product data
PCK2002
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0: SDRAM Output active/inactive register
1 = enable; 0 = disable
BIT(S)
AFFECTED PIN
PIN NO.
PIN NAME
CONTROL FUNCTION
7
18
BUF_OUT7
Clock Output Disable
6
17
BUF_OUT6
Clock Output Disable
5
14
BUF_OUT5
Clock Output Disable
4
13
BUF_OUT4
Clock Output Disable
3
9
BUF_OUT3
Clock Output Disable
2
8
BUF_OUT2
Clock Output Disable
1
5
BUF_OUT1
Clock Output Disable
0
4
BUF_OUT0
Clock Output Disable
NOTE:
1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.
BIT CONTROL
0
1
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Byte 1: SDRAM Output active/inactive register
1 = enable; 0 = disable
BIT(S)
AFFECTED PIN
PIN NO.
PIN NAME
CONTROL FUNCTION
7
45
BUF_OUT15
Clock Output Disable
6
44
BUF_OUT14
Clock Output Disable
5
41
BUF_OUT13
Clock Output Disable
4
40
BUF_OUT12
Clock Output Disable
3
36
BUF_OUT11
Clock Output Disable
2
35
BUF_OUT10
Clock Output Disable
1
32
BUF_OUT9
Clock Output Disable
0
31
BUF_OUT8
Clock Output Disable
NOTE:
1. At power up all SDRAM outputs are enabled and active. Program all reserved bits to “0”.
BIT CONTROL
0
1
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
Low
Active
2001 Jul 19
7
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