PCF8579T Ver la hoja de datos (PDF) - NXP Semiconductors.
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PCF8579T Datasheet PDF : 41 Pages
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NXP Semiconductors
PCF8579
LCD column driver for dot matrix graphic displays
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
VSO56
SDA
SCL
SYNC
CLK
VSS
TEST[1]
SA0
A3 to A0
VDD
n.c.[2]
1
2
3
4
5
6
7
8 to 11
12
13
V3, V4
VLCD
C39 to C0
14, 15
16
17 to 56
Description
LQFP64,
TQFP64
7
I2C-bus serial data input/output
8
I2C-bus serial clock input
9
cascade synchronization output
10
external clock input/output
11
ground
12
test pin
13
I2C-bus slave address input (bit 0)
14, 16 to 18 I2C-bus subaddress inputs
20
supply voltage
15, 19, 21, 25 not connected
to 29, 34
22, 23
LCD bias voltage inputs
24
LCD supply voltage
30 to 33, 35 LCD column driver outputs
to 64, 1 to 6
[1] The TEST pin must be connected to VSS.
[2] Do not connect, these pins are reserved.
8. Functional description
The PCF8579 column driver is designed for use with the PCF8578. Together they form a
general purpose LCD dot matrix chip set.
Typically up to 16 PCF8579s may be used with one PCF8578 (examples of cascading the
devices see Table 16, Figure 21, Figure 22, Figure 23 and Figure 24). Each of the
PCF8579s is identified by a unique 4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when using two I2C-bus slave
addresses. The two slave addresses are set by the logic level on input SA0.
8.1 Power-on reset
At power-on the PCF8579 resets to a defined starting condition as follows:
1. Display blank (in conjunction with PCF8578)
2. 1:32 multiplex rate
3. Start bank 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized
PCF8579_5
Product data sheet
Rev. 05 — 11 May 2009
© NXP B.V. 2009. All rights reserved.
7 of 41
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