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PCF2113 Datasheet PDF : 65 Pages
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NXP Semiconductors
PCF2113x
LCD controllers/drivers
Table 5. Pin and bonding pad description …continued
All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see
Figure 3).
Symbol
Pin
Type Pad
X (µm)
Y (µm)
Description
C1
77
O
86
−1 630
1 185
LCD column driver output
R8
78
O
87
−1 630
1 115
LCD row driver output
R7
79
O
88
−1 630
1 045
LCD row driver output
R6
80
O
89
−1 630
975
LCD row driver output
R5
81
O
90
−1 630
905
LCD row driver output
R4
82
O
91
−1 630
835
LCD row driver output
R3
83
O
92
−1 630
765
LCD row driver output
R2
84
O
93
−1 630
695
LCD row driver output
R1
85
O
94
−1 630
625
LCD row driver output
R17
86
O
95
−1 630
555
LCD row driver output
SCL
87
I
96
−1 630
375
I2C-bus serial clock input
[4]
SDA
88
I/O
97
−1 630
305
I2C-bus serial data input/output
[4]
E
89
I
98
−1 630
85
data bus clock input
[4]
RS
90
I
99
−1 630
−15
register select input
R/W
91
I
100
−1 630
−115
read or write input
DB7
92
I/O
101
−1 630
−215
8-bit bidirectional bus bit 7
[5]
DB6
93
I/O
102
−1 630
−315
8-bit bidirectional bus bit 6
DB5
94
I/O
103
−1 630
−415
8-bit bidirectional bus bit 5
DB4
95
I/O
104
−1 630
−515
8-bit bidirectional bus bit 4
DB3/SA0
96
I/O
105
−1 630
−615
8-bit bidirectional bus bit 3 or I2C-bus
[4][5]
address input
DB2
97
I/O
106
−1 630
−71 5
8-bit bidirectional bus bit 2
DB1
98
I/O
107
−1 630
−815
8-bit bidirectional bus bit 1
DB0
99
I/O
108
−1 630
−915
8-bit bidirectional bus bit 0
VDD2
100
P
109
−1 630
−1 015
supply voltage 2 for VLCD generator
[6]
VDD3
-
P
110
−1 630
−1 235
supply voltage 3 for VLCD generator
[3][6]
dummy pad 7 -
-
111
−1 630
−1 395
-
dummy pad 8 -
-
112
−1465
−1 550
-
[1] When the on-chip oscillator is used this pad must be connected to VDD1.
[2] When VLCD is generated internally, pins VLCDIN, VLCDOUT and VLCDSENSE must be connected together. When an external VLCD is
supplied, this should be done via VLCDIN. In this case only pins VLCDOUT and VLCDSENSE must be connected together.
[3] In the LQFP100 version this signal is connected internally and is not accessible.
[4] When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode pins DB7 to DB0 must be connected to
VDD1 or left open-circuit.
When the parallel bus is used, the pins SCL and SDA must be connected to pin VSS1 or pin VDD1; they must not be left open-circuit.
When the 4-bit interface is used without reading out from the PCF2113x (bit R/W is set permanently to logic 0), the unused ports DB0 to
DB3 can either be connected to VSS1 or VDD1 instead of leaving them open-circuit.
[5] DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the four higher order
lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations (see Table note 4).
[6] VDD2 and VDD3 must always be equal.
PCF2113_FAM_4
Product data sheet
Rev. 04 — 4 March 2008
© NXP B.V. 2008. All rights reserved.
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