PCF85103C-2(2002) Ver la hoja de datos (PDF) - Philips Electronics

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PCF85103C-2
(Rev.:2002)

256 × 8-bit CMOS EEPROM with I2C-bus interface

Philips Electronics 

Philips Semiconductors

PCF85103C-2

256 × 8-bit CMOS EEPROM with I2C-bus interface

The master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge

clock pulse in such a way that the SDA line is stable LOW during the HIGH period of

the acknowledge related clock pulse.

Set-up and hold times must be taken into account. A master receiver must signal an

end of data to the slave transmitter by not generating an acknowledge on the last byte

that has been clocked out of the slave. In this event, the transmitter must leave the

data line HIGH to enable the master generation of the STOP condition.

8.1.3 Device addressing

Following a START condition, the bus master must output the address of the slave it

is accessing. The address of the PCF85103C-2 is shown in Figure 4. To conserve

power, no internal pull-up resistors are incorporated on the hardware selectable pins

and they must be connected to either VDD or VSS.

0 0 1 0 A2 A1 A0 R/W

Fig 4. Slave address.

FIXED

HARDWARE

SELECTABLE

002aaa253

The last bit of the slave address defines the operation to be performed. When set to

logic 1, a read operation is selected, while a logic 0 selects a write operation.

8.1.4 Write operations

Byte/word write: For a write operation, the PCF85103C-2 requires a second

address field. This address field is a word address providing access to the 256 words

of memory. Upon receipt of the word address, the PCF85103C-2 responds with an

acknowledge and awaits the next eight bits of data, again responding with an

acknowledge. Word address is automatically incremented. The master can now

terminate the transfer by generating a STOP condition or transmit up to six more

bytes of data and then terminate by generating a STOP condition.

After this STOP condition, the E/W cycle starts and the bus is free for another

transmission. Its duration is 10 ms per byte.

During the E/W cycle the slave receiver does not send an acknowledge bit if

addressed via the I2C-bus.

9397 750 09646

Product data

Rev. 02 — 09 May 2002

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

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