PCF8558 Ver la hoja de datos (PDF) - Philips Electronics

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PCF8558

Universal LCD driver for small graphic panels

Philips Electronics 

Philips Semiconductors

Universal LCD driver for small graphic

panels

Objective specification

PCF8558

I2C-BUS PROTOCOL

Two 7-bit slave addresses (0111100 and 0111101) are

reserved for both the PCF8558. The least-significant bit of

the slave address is set by connecting input SA0 to

either 0 (VSS) or 1 (VDD). Therefore, two PCF8558 can be

used on the same I2C-bus allowing displays of up to

80 × 101 or 40 × 202 dots to be driven.

The I2C-bus protocol is shown in Fig.6.

All communications are initiated with a START condition

(S) from the I2C-bus master, which is followed by the

desired slave address and write bit. All devices with this

slave address acknowledge in parallel. All other devices

ignore the bus transfer.

In write mode (indicated by setting the read/write bit LOW)

one or more commands follow the slave address

acknowledgement. The commands are also

acknowledged by all addressed devices on the bus.

The last command must clear the continuation bit C. After

the last command a series of data bytes may follow.

The acknowledgement after each byte is made only by the

addressed device. After the last data byte has been

acknowledged, the I2C-bus master issues a STOP

condition (P).

For PCF8558, no read mode is provided.

Display bytes are written into the RAM at the address

specified by the data pointer and subaddress counter.

Both the data pointer and subaddress counter are

automatically incremented, enabling a stream of data to be

transferred to the DDRAM.

The instruction format is composed of I2C-bus slave

address followed by one command byte, one X address

pointer, followed by any number of data bytes.

Command execution/storing of data takes place during the

acknowledge cycle.

Definitions

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt to

control the bus at the same time. The I2C-bus can

accommodate this without data los/contention.

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

R/W

handbook, full pagewidth

SA

S011110A C

OK

slave address

COMMAND

A

A

A

C

X ADDRESS

C DISPLAY DATA C P

K

K

K

N ≥ 0 bytes

MGG563

Fig.6 I2C-bus protocol.

1998 Apr 07

9

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