PCF2119VU/2 Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
PCF2119VU/2 Datasheet PDF : 68 Pages
| |||
Philips Semiconductors
LCD controllers/drivers
Product specification
PCF2119X
8.6 Function set
8.6.1 DL (PARALLEL MODE ONLY)
Sets interface data width. Data is sent or received in bytes
(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)
when DL = 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit
application DB3 to DB0 should be left open-circuit (internal
pull-ups). Hence in the first ‘function set’ instruction after
power-on, M, SL and H are set to logic 1. A second
‘function set’ must then be sent (2 nibbles) to set M,
SL and H to their required values.
‘Function set’ from the I2C-bus interface sets the DL bit to
logic 1.
8.6.2 M
Selects either 1-line by 32 display (M = 0) or 2-line by
16 display (M = 1).
8.6.3 SL
Selects MUX 1 : 9, 1-line by 16 display (independent of
M and L). Only rows 1 to 8 and 17 are to be used. All other
rows must be left open-circuit. The DDRAM map is the
same as in the 2-line by 16 display mode, however, the
second line is not displayable.
8.6.4 H
When H = 0 the chip can be programmed via the standard
11 instruction codes used in the PCF2116 and other LCD
controllers.
When H = 1 the extended range of instructions will be
used. These are mainly for controlling the display
configuration and the icons.
8.7 Set CGRAM address
‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM
address ACG into the address counter (binary A5 to A0).
Data can then be written to or read from the CGRAM.
Attention: the CGRAM address uses the same address
register as the DDRAM address and consists of 7 bits
(binary A6 to A0). With the ‘set CGRAM address’
command, only bits 5 to 0 are set. Bit 6 can be set using
the ‘set DDRAM address’ command first, or by using the
auto-increment feature during CGRAM write. All bits 6 to 0
can be read using the ‘read busy flag’ and ‘read address’
command.
When writing to the lower part of the CGRAM, ensure that
bit 6 of the address is not set (e.g. by an earlier DDRAM
write or read action).
8.8 Set DDRAM address
‘Set DDRAM address’ sets the DDRAM address ADD into
the address counter (binary A6 to A0). Data can then be
written to or read from the DDRAM.
8.9 Read busy flag and read address
‘Read busy flag’ and ‘read address’ read the Busy Flag
(BF) and Address Counter (AC). BF = 1 indicates that an
internal operation is in progress. The next instruction will
not be executed until BF = 0. It is recommended that the
BF status is checked before the next write operation is
executed.
At the same time, the value of the address counter
expressed in binary A6 to A0 is read out. The address
counter is used by both CGRAM and DDRAM, and its
value is determined by the previous instruction.
8.10 Write data to CGRAM or DDRAM
‘Write data’ writes binary 8-bit data D7 to D0 to the
CGRAM or the DDRAM.
Whether the CGRAM or DDRAM is to be written into is
determined by the previous ‘set CGRAM address’ or ‘set
DDRAM address’ command. After writing, the address
automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D4 to D0 of
CGRAM data are valid, bits D7 to D5 are ‘don’t care’.
8.11 Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data D7 to D0 from the
CGRAM or DDRAM.
The most recent ‘set address’ command determines
whether the CGRAM or DDRAM is to be read.
The ‘read data’ instruction gates the content of the Data
Register (DR) to the bus while E is HIGH. After E goes
LOW again, internal operation increments (or decrements)
the AC and stores RAM data corresponding to the new AC
into the DR.
There are only three instructions that update the data
register:
• ‘set CGRAM address’
• ‘set DDRAM address’
• ‘read data’ from CGRAM or DDRAM.
Other instructions (e.g. ‘write data’, ‘cursor/display shift’,
‘clear display’ and ‘return home’) do not modify the data
register content.
2003 Jan 30
29
Share Link: 