PCA9549 Ver la hoja de datos (PDF) - NXP Semiconductors.
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PCA9549 Datasheet PDF : 25 Pages
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NXP Semiconductors
PCA9549
Octal bus switch with individually I2C-bus controlled enables
Table 4. Control register
Write = channel selection; read = channel status.
B7
B6
B5
B4
B3
B2
B1
B0 Command
0 bit 1 disabled
X
X
X
X
X
X
X
1 bit 1 enabled
0
bit 2 disabled
X
X
X
X
X
X
X
1
bit 2 enabled
0
bit 3 disabled
X
X
X
X
X
X
X
1
bit 3 enabled
0
bit 4 disabled
X
X
X
X
X
X
X
1
bit 4 enabled
0
bit 5 disabled
X
X
X
X
X
X
X
1
bit 5 enabled
0
bit 6 disabled
X
X
X
X
X
X
X
1
bit 6 enabled
0
bit 7 disabled
X
X
X
X
X
X
X
1
bit 7 enabled
0
bit 8 disabled
X
X
X
X
X
X
X
1
bit 8 enabled
[1] Several bits can be enabled at the same time. For example, B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1,
B1 = 0, B0 = 0, means that bit 8, bit 6, bit 5, bit 2, and bit 1 are disabled and bit 7, bit 4, and bit 3 are
enabled.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9549 will reset its
registers and I2C-bus state machine and will open all bits. The RESET input must be
connected to VDD through a pull-up resistor.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9549 in
a reset state until VDD has reached VPOR. At this point, the reset condition is released and
the PCA9549 registers and I2C-bus state machine are initialized to their default states, all
zeroes causing all the bits to be open (high-impedance state).
6.5 CBT characteristic over VDD range
The bus switch is optimized at 5.0 V but can operate over the entire supply range with
lower Vo(sw) voltage and higher gate resistance.
PCA9549_2
Product data sheet
Rev. 02 — 13 July 2009
© NXP B.V. 2009. All rights reserved.
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