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PCA9539 Datasheet PDF : 31 Pages
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NXP Semiconductors
PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.5 Registers 6 and 7: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. At reset, the device's ports are inputs.
Table 11.
Bit
Symbol
Default
Configuration port 0 register
7
6
5
C0.7
C0.6
C0.5
1
1
1
4
C0.4
1
3
C0.3
1
2
C0.2
1
1
C0.1
1
0
C0.0
1
Table 12.
Bit
Symbol
Default
Configuration port 1 register
7
6
5
C1.7
C1.6
C1.5
1
1
1
4
C1.4
1
3
C1.3
1
2
C1.2
1
1
C1.1
1
0
C1.0
1
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9539; PCA9539R
in a reset condition until VDD has reached VPOR. At that point, the reset condition is
released and the PCA9539; PCA9539R registers and SMBus state machine will initialize
to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In
the PCA9539 the registers and SMBus/I2C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input typically requires a pull-up to
VDD. In the PCA9539R, only the device state machine is initialized. The internal
general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin
will only reset the I2C-bus interface should it be stuck LOW to regain access to the
I2C-bus. This allows the I/O pins to retain their last configured state so that they can keep
any lines in their previously defined state and not cause system errors while the I2C-bus is
being restored.
6.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of
the Output port register. Care should be exercised if an external voltage is applied to an
I/O configured as an output because of the low-impedance path that exists between the
pin and either VDD or VSS.
PCA9539_PCA9539R_5
Product data sheet
Rev. 05 — 28 July 2008
© NXP B.V. 2008. All rights reserved.
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