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PCA9502 Datasheet PDF : 25 Pages
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NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
7.2 Interrupts
The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna)
enables interrupts due to I/O pin change of state, and the IRQ signal in response to an
interrupt generation.
8. Register descriptions
The programming combinations for register selection are shown in Table 5.
Table 5. Register map - read/write properties
Register name Read mode
IODir
I/O pin direction
IOState
I/O pin states
IOIntEna
I/O interrupt enable register
IOControl
I/O pins control
Write mode
I/O pin direction
n/a
I/O interrupt enable register
I/O pins control
Table 6. PCA9502 internal registers
Register
address
Register
Bit 7
Bit 6
General Register Set
0x0A[1] IODir
bit 7
0x0B[1] IOState bit 7
0x0C[1] IOIntEna bit 7
0x0D[1] reserved reserved
[2]
[2]
bit 6
bit 6
bit 6
reserved
[2]
0x0E[1] IOControl reserved reserved
[2]
[2]
Bit 5
bit 5
bit 5
bit 5
reserved
[2]
reserved
[2]
Bit 4
bit 4
bit 4
bit 4
reserved
[2]
reserved
[2]
Bit 3
bit 3
bit 3
bit 3
reserved
[2]
SReset
Bit 2
bit 2
bit 2
bit 2
reserved
[2]
reserved
[2]
Bit 1
bit 1
bit 1
bit 1
reserved
[2]
reserved
[2]
Bit 0
bit 0
bit 0
bit 0
reserved
[2]
IOLatch
R/W
R/W
R/W
R/W
R/W
[1] Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write).
[2] These bits are reserved and should be set to 0.
8.1 Programmable I/O pins Direction register (IODir)
This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to
GPIO7.
Table 7.
Bit
7:0
IODir register (address 0x0A) bit description
Symbol
Description
IODir
set GPIO pins 7:0 to input or output
0 = input
1 = output
Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending
interrupt will be cleared, that is, the interrupt signal will be negated.
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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