PCA9502 Ver la hoja de datos (PDF) - Philips Electronics
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PCA9502 Datasheet PDF : 25 Pages
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NXP Semiconductors
6. Pinning information
6.1 Pinning
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
terminal 1
index area
RESET 1
VDD 2
VDD 3
VDD 4
A0 5
A1 6
PCA9502BS
18 GPIO4
17 VSS
16 GPIO3
15 GPIO2
14 GPIO1
13 GPIO0
terminal 1
index area
RESET 1
VDD 2
VDD 3
VSS 4
CS 5
SI 6
PCA9502BS
18 GPIO4
17 VSS
16 GPIO3
15 GPIO2
14 GPIO1
13 GPIO0
002aab839
Transparent top view
a. I2C-bus interface
Fig 3. Pin configuration for HVQFN24
Transparent top view
b. SPI interface
002aab840
6.2 Pin description
Table 2. Pin description
Symbol
Pin
Type Description
RESET
1
I
device hardware reset (active LOW)[1]
VDD
2, 3, 11, -
power supply
22, 24
I2C/SPI
4
I
I2C-bus or SPI interface select. I2C-bus interface is selected if this
pin is at logic HIGH. SPI interface is selected if this pin is at logic
LOW.
CS/A0
5
I
SPI chip select or I2C-bus device address select A0. If SPI
configuration is selected by I2C/SPI pin, this pin is the SPI chip
select pin (Schmitt trigger, active LOW). If I2C-bus configuration
is selected by I2C/SPI pin, this pin along with A1 pin allows user
to change the device’s base address.
SI/A1
6
I
SPI data input pin or I2C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data input
pin. If I2C-bus configuration is selected by I2C/SPI pin, this pin
along with A0 pin allows user to change the device’s base
address. To select the device address, please refer to Table 11.
SO
7
O SPI data output pin. If SPI configuration is selected by I2C/SPI
pin, this is a 3-stateable output pin. If I2C-bus configuration is
selected by I2C/SPI pin, this pin function is undefined and must
be left as n.c. (not connected).
SCL/SCLK 8
I
I2C-bus or SPI input clock.
SDA
9
I/O I2C-bus data input/output, open-drain if I2C-bus configuration is
selected by I2C/SPI pin. If SPI configuration is selected then this
pin is an undefined pin and must be connected to VSS.
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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