SAB-C502-2R Ver la hoja de datos (PDF) - Infineon Technologies

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SAB-C502-2R

8-Bit CMOS Microcontroller

Infineon Technologies 

C502

Pin Definitions and Functions (cont’d)

Symbol

RESET

ALE

EA

P0.0 – P0.7

VSS

VCC

N.C.

Pin Number

P-LCC-44 P-DIP-40

10

9

33

30

35

31

43–36

39–32

22

20

44

40

1, 12,

–

23, 34

I/O*) Function

I

RESET

A high level on this pin for two machine cycles

while the oscillator is running resets the

device. An internal diffused resistor to VSS

permits power-on reset using only an external

capacitor to VCC.

O The Address Latch Enable

output is used for latching the low-byte of the

address into external memory during normal

operation. It is activated every six oscillator

periodes except during an external data

memory access.

I

External Access Enable

When held at high level, instructions are

fetched from the internal ROM (SAB-C502-2R

only) when the PC is less than 4000H. When

held at low level, the SAB-C502 fetches all

instructions from external program memory.

For the SAB-C502-L this pin must be tied low.

I/O Port 0

is an 8-bit open-drain bidirectional I/O port.

Port 0 pins that have 1s written to them float,

and in that state can be used as high-

impedance inputs. Port 0 is also the

multiplexed low-order address and data bus

during accesses to external program or data

memory. In this application it uses strong

internal pull-up resistors when issuing 1s.

Port 0 also outputs the code bytes during

program verification in the SAB-C502-2R.

External pull-up resistors are required during

program verification.

– Circuit ground potential

– Supply terminal for all operating modes

– No connection

*) I = Input

O = Output

Semiconductor Group

10

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