PBL3766QN Ver la hoja de datos (PDF) - Ericsson

Número de pieza

componentes Descripción

Fabricante

PBL3766QN

Subscriber Line Interface Circuit

Ericsson  

PBL 3766

PLCC DIP Symbol

11 8 DET

Description

Detector output. Inputs C1 and C2 select one of the two detectors to be connected to the DET output. A

logic low level at the enabled (refer to E0) DET output indicates a triggered detector condition. The DET

output is open collector with internal pull-up resistor (approximately 15 kohms) to VCC.

12 9 C2

13 10 C1

C1 and C2 are TTL compatible inputs controlling the SLIC operating states. Refer to section

Control inputs for details.

14 11 RDC

Dc loop feed is programmed by one resistor connected from this pin to the receive summing node (RSN)

A decoupling capacitor, CDC, connected from RDC to GND removes noise and other ac signals from the

battery feed control loop.

15

-

NC

No internal connection. Note 1.

16 12 RSN

Receive summing node. 1000 times the current (dc and ac) flowing into this pin equals the metallic

(transversal) current flowing from RINGX to TIPX. Programming networks for constant dc loop current,

two-wire impedance and receive gain connect to the receive summing node.

17

-

VBAT

Refer to PLCC, terminal 6 description.

18 13 VEE

-5V power supply.

19 14 VTX

Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is

reproduced as an unbalanced GND referenced signal at VTX with a gain of one. The two-wire termina-

ting impedance programming network connects between VTX and RSN.

20 15 HPT

21 16 HPR

22 19 RD

Tip side of ac/dc separation capacitor C . Other end of C connects to pin, HPR.

HP

HP

Ring side of ac/dc separation capacitor C . Other end of C capacitor connects to pin, HPT.

HP

HP

Loop current detector programming resistor RD connects from RD to VEE. An optional filter capacitor CD

may be connected between terminal RD and ground. With the RD pin left open, the loop current detect

threshold is internally set to 8.0 mA. Refer to section Loop monitoring functions for additional information.

23 20 DT

DT is the non-inverting ring trip comparator input. The inverting comparator input is internally connected

to VEE. With DT more negative than the inverting input, the detector output, DET, is at logic level low,

indicating off-hook condition. The ring trip network connects to the DT input.

24

-

VBAT

Refer to PLCC, terminal 6 description.

25

-

NC

No internal connection. Note 1.

26

-

TIPXSense

TIPX is internally connected to TIPX. TIPX is used during manufacturing, but requires no

Sense

Sense

connection in SLIC applications, i.e. leave open.

27 21 TIPX

The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage

28 22 RINGX protection components and ring relay (and optional test relays).

Notes

1. Terminals marked NC are not internally connected to the chip. These terminals may be connected to ground for shielding.

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