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MTD981AG

10/100 Ethernet Transceiver

Myson Century Inc 

MYSON

TECHNOLOGY

MTD981A

Before any transaction, the station must send 32 continuous logic "1" on MDIO to establish synchronization.

Figure 1 shows the read and write operation. The start code is "01" followed by an op code, either "01" for

read or "10" for write. For read operation, the device address must match the address of the target PHY

device. For write operation, the address may be all zero or match a specific PHY address. Turnaround cycle

is an idle cycle consists of two bit times between the register address field and data field in order to avoid

conflict. For reading, no device drive MDIO in the first bit time, PHY drive "0" in the second bit time. For

writing, station drive "10" during the idle cycle.

3. 10BASE-T

When configured to run in 10BASE-T mode, either through hardware configuration, software, or Auto-

Negotiation, the MTD981A will support all the functions specified in IEEE 802.3 Standard for 10BASE-T

(Clause 14).

3.1 Transmit Function

In 10BASE-T mode, the transmit function uses parallel-to-serial logic to convert the 4-bit transmit data into a

serial data stream. This serial data stream is Manchester-encoded and then output through the

waveshaping driver. Filtering is performed in silicon to reduce EMI emission. TXOP/TXON can be

connected directly to a standard transformer. External filtering modules are not needed

3.2 Receive Function

In 10BASE-T mode, the signals at RXIP/RXIN first pass a smart squelch circuit. A Manchester decoder and

a serial-to-parallel converter then follow to generate the 4-bit nibble in MII interface. The squelch level of the

smart squelch circuit drops to half its threshold value after unsquelch to allow reception of minimum

amplitude signals to mitigate carrier fade in the event of worst case signal attenuation.

3.3 Link Monitor

In 10BASE-T mode, link pulse detection circuit will constantly monitor the RXIP/RXIN pins for the presence

of valid link pulses. In the absence of valid link pulses, the LINK led will deassert.

4. 100BASE-TX

When configured to run in 100BASE-T mode, either through hardware configuration, software, or Auto-

Negotiation, the MTD981A will support all the functions specified in IEEE 802.3 Standard for 10BASE-TX.

4.1 Transmit Function

In 100BASE-TX mode, the transmit function converts synchronous 4-bit data nibbles from the MII to a 125-

Mbps differential serial data stream in MLT-3 format. The entire operation is synchronous to a 25-MHz clock

and a 125-MHz clock. Both clocks are generated by an on-chip PLL clock synthesizer that is locked to an

external 25-MHz clock source. There are three functional blocks in the transmit function: 4B/5B encoder,

scrambler, and MLT-3 output driver. The 4B/5B encoder, defined in IEEE 802.3 Clause 24, converts 4-bit

raw data to 5-bit code-group. It also inserts the stream boundary delimiters (/J/K/ and /T/R/) at the beginning

and end of the data stream as appropriate. The 4B/5B encoded data has repetitive patterns which result in

peaks in the RF spectrum. The peaks in the radiated signal are reduced significantly by scrambling the

transmitted signal. The scrambler, defined by the TP-PMD Stream Cipher function, encodes a plain text

NRZ bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function:

X[n] = X[n-11] + X[n-9] (modulo 2)

The scrambler reduces peak emission by randomly spreading the signal energy over the transmit frequency

range, thus eliminating peaks at a single frequency. The scrambled NRZ data stream is then converted to

MLT-3 encoded data and then output to the UTP-5 cable. The MLT-3 is a tri-level signal. The presence of a

transition has a logical value of 1 and the lack of a transition has a logical value of 0. The benefit of MLT-3 is

that it reduces the the maximum frequency from 62.5 MHz to 31.25 MHz.

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MTD981A Revision 1.2 02/19/2001

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