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MTD981AG

10/100 Ethernet Transceiver

Myson Century Inc 

MYSON

TECHNOLOGY

MTD981A

FUNCTIONAL DESCRIPTIONS

1. Media Independent Interface (MII)

The MTD981A implements an IEEE 802.3u Clause 22 compliant MII interface described as follows. The

interface signals can be grouped into transmit, receive, and status. The transmit data signals comprise

TXD[3:0], TXEN, TXER, and TXCLK. TXD[3:0] are the nibble size data path, TXEN signals the presence of

data on TXD[3:0], TXER indicates substitution of data with the HALT symbol, and TXCLK carries the

transmit clock that synchronizes all the transmit signals. The receive data signals also include seven signals,

RXD[3:0], RXDV, RXER, and RXCLK. RXD[3:0] are the nibble size data path, RXDV signals the presence

of data on RXD[3:0], RXER indicates the validity of data, and RXCLK carries the receive clock. Depending

on the operation mode, RXCLK signal is generated by the clock recovery module of either the 100Base-X or

10Base-T receiver. Two status signals, COL and CRS, are generated in the MTD981A to indicate Collison

status and Carrier Sense status to the MAC.

2. Serial Management Interface (SMI)

The MTD981A implements a Serial Management Interface (SMI) used both to obtain status from and to

configure the PHY. This mechanism corresponds to the MII Spec for 100BASE-X (Clause 22). The SMI

interface consists of two signals, MDC and MDIO. MDC is a clock input to the PHY and is used to latch data

and instructions for the PHY. The clock rate can run up to 2.5MHz. MDIO is bi-directional and is used to

write instruction to, write data to, or read data from PHY. Each data bit is latched either in or out on the

rising edge of MDC. MDC/MDIO are a common signal pair to up to 32 PHYs. Therefore, each PHY needs

its unique address. The MTD981A uses 5 bits as PHY address. The address is latched into internal register

during reset from the pin setting. The SMI interface supports registers 0 through 6. Additional “vendor-

specific” registers are implemented. All the registers are described in the register section. The access

method of these registers is described as follows.

MDC

MIDIO z

z

(STA)

MDIO

z

z

(PHY)

z 0 1 1 0 0 1 1 0 0 0 0 0 0z1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 z

idle

start opcode

phyaddr

regaddr

TA

register data

idle

Typical MII Read Operation

MDC

MIDIO z

z

(STA)

01010110000000100000000000000000z

idle

start opcode

phyaddr

regaddr

TA

register data

idle

Typical MII Write Operation

Figure 1. MII Read/Write operation

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MTD981A Revision 1.2 02/19/2001

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