PALCE22V10 Ver la hoja de datos (PDF) - Lattice Semiconductor
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PALCE22V10 Datasheet PDF : 34 Pages
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AR
DQ
CLK
Q
SP
S0 = 0
S1 = 0
S0 = 0
S1 = 1
a. Registered/active low
AR
S0 = 1
S1 = 0
DQ
CLK
Q
SP
b. Combinatorial/active low
S0 = 1
S1 = 1
c. Registered/active high
d. Combinatorial/active high
Figure 2. Macrocell Configuration Options
16564E-005
Programmable Three-State Outputs
Each output has a three-state output buffer with three-state control. A product term controls the
buffer, allowing enable and disable to be a function of any product of device inputs or output
feedback. The combinatorial output provides a bi-directional I/O pin, and may be configured as
a dedicated input if the buffer is always disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high or active low, either to match output
signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered
and combinatorial outputs. Selection is automatic, based on the design specification and pin
definitions. If the pin definition and output equation have the same polarity, the output is
programmed to be active high (S0 = 1).
Preset/Reset
For initialization, the PALCE22V10 has preset and reset product terms. These terms are connected
to all registered outputs. When the synchronous preset (SP) product term is asserted high, the
output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the
asynchronous reset (AR) product term is asserted high, the output registers will be immediately
loaded with a LOW independent of the clock.
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PALCE22V10 and PALCE22V10Z Families
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