M35080 Ver la hoja de datos (PDF) - STMicroelectronics
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M35080 Datasheet PDF : 18 Pages
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Figure 12. Page Write Operation Sequence
M35080
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
C
INSTRUCTION
16 BIT ADDRESS
DATA BYTE 1
D
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
D
7654321076543210
6543210
AI01796
Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.
2. The number of clock pulses must be a multiple of 8. Otherwise, the write is aborted.
POWER ON STATE
After power-on, the memory device is in the follow-
ing state:
– low power stand-by state
– deselected (after power-on, a high-to-low transi-
tion is required on the S input before any opera-
tions can be started).
– the WEL bit is reset
– the SRWD, BP1 and BP0 bits of the status reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
Table 8. Initial Status Register Format
b7
b0
0
001
0
0
0
0
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state. With the exception of the first 32
bytes, all data bits are set to ‘1’, and hence all data
bytes are at FFh. The first 32 bytes are set to all
‘0’s, and hence the first 16 words at 0000h.
The status register bits are initialized to ‘0’, except
for bit b4, which is set to ‘1’, as shown in Table 8.
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