ST24W08M5TR(2002) Ver la hoja de datos (PDF) - STMicroelectronics

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ST24W08M5TR
(Rev.:2002)

8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection

STMicroelectronics 

ST24/25C08, ST24/25W08

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

ST24x08

ST25x08

PRE 1

NC 2

8 VCC

7 MODE/WC

E3

6 SCL

VSS 4

5 SDA

AI00861E

PRE

NC

E

VSS

ST24x08

ST25x08

1

8

2

7

3

6

4

5

AI01073E

VCC

MODE/WC

SCL

SDA

Warning: NC = Not Connected.

Warning: NC = Not Connected.

Table 2. Absolute Maximum Ratings (1)

Symbol

TA

TSTG

TLEAD

Parameter

Ambient Operating Temperature

Storage Temperature

Lead Temperature, Soldering

(SO8 package)

(PSDIP8 package)

40 sec

10 sec

Value

Unit

–40 to 125

°C

–65 to 150

°C

215

260

°C

VIO

Input or Output Voltages

–0.6 to 6.5

V

VCC

VESD

Supply Voltage

Electrostatic Discharge Voltage (Human Body model) (2)

Electrostatic Discharge Voltage (Machine model) (3)

–0.3 to 6.5

V

4000

V

500

V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

DESCRIPTION (cont’d)

The ST24/25x08 are 8 Kbit electrically erasable

programmable memories (EEPROM), organized

as 4 blocks of 256 x8 bits. They are manufactured

in STMicroelectronics’s Hi-Endurance Advanced

CMOS technology which guarantees an endur-

ance of one million erase/write cycles with a data

retention of 40 years.

Both Plastic Dual-in-Line and Plastic Small Outline

packages are available.

The memories are compatible with the I2C stand-

ard, two wire serial interface which uses a bi-dire-c

tional data bus and serial clock. The memories

carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I2C bus defini-

tion. This is used together with 1 chip enable input

(E) so that up to 2 x 8K devices may be attached

to the I2C bus and selected individually. The memo-

ries behave as a slave device in the I2C protocol

with all memory operations synchronized by the

serial clock. Read and write operations are initiated

by a START condition generated by the bus master.

The START condition is followed by a stream of 7

bits (identification code 1010), plus one read/write

bit and terminated by an acknowledge bit.

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