P90CE201 Ver la hoja de datos (PDF) - Philips Electronics
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P90CE201 Datasheet PDF : 77 Pages
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Philips Semiconductors
16-bit microcontroller
6.2.4 LATCHED INTERRUPT REGISTER n (LIRn)
bit 7
bit 6
bit 5
bit 4
INTNC1
INTNC0
AVN
−
bit 3
PIR
bit 2
IPL2
Product specification
P90CE201
bit 1
IPL1
bit 0
IPL0
Fig.12 Latched Interrupt Register n (LIRn).
Table 6 Description of LIRn bits.
SYMBOL
INTNC1
INTNC0
AVN
−
PIR
IPL2
IPL1
IPL0
BIT
LIRn.7
LIRn.6
LIRn.5
LIRn.4
LIRn.3
LIRn.2
LIRn.1
LIRn.0
FUNCTION
Interrupt Control. These two bits enable/disable the external interrupt INTNn, or
select the pin as an I/O port. See Table 7.
Autovector. When AVN = 0; INTNn is an autovectored interrupt and the processor
calculates the appropriate vector from a fixed vector table. This is also the default
value. When AVN = 1; INTNn is a vectored interrupt and the peripheral must provide
an 8-bit vector number.
Not used; reserved
Pending Interrupt Request. If PIR = 1; then a valid interrupt request has been
detected. It is automatically reset by the interrupt acknowledge cycle from the
CPU. If PIR = 0; there is no pending interrupt request; this is also the default value.
PIR can be set or reset by software by writing a logic 1 or logic 0 respectively to PIRn.
Interrupt Priority Level. These three bits select the interrupt priority level for the
external interrupt INTNn. See Table 8.
Table 7 Interrupt INTNn control.
INTNC1
0
0
1
1
INTNC0
0
1
0
1
INTERRUPT CONTROL
Interrupt disabled; this is also the default value.
interrupt enabled
Interrupt pin is selected as an I/O port.
Reserved
Table 8 Selection of interrupt priority level.
IPL2
0
0
0
0
1
1
1
1
IPL1
0
0
1
1
0
0
1
1
IPL0
0
1
0
1
0
1
0
1
PRIORITY LEVEL
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
August 1993
20
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