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P89LPC9321

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

4. Block diagram

P89LPC9321

8-bit microcontroller with accelerated two-clock 80C51 core

P89LPC9321

ACCELERATED 2-CLOCK 80C51 CPU

P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

CRYSTAL

OR

RESONATOR

XTAL1

XTAL2

8 kB

CODE FLASH

256-BYTE

DATA RAM

512-BYTE

AUXILIARY RAM

internal bus

512-BYTE

DATA EEPROM

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

clock

CONFIGURABLE

OSCILLATOR

ON-CHIP RC

OSCILLATOR

WITH CLOCK

DOUBLER

Fig 1. Block diagram

UART

I2C-BUS

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0

TIMER 1

ANALOG

COMPARATORS

(PGA1)

CCU (CAPTURE/

COMPARE UNIT)

TXD

RXD

SCL

SDA

SPICLK

MOSI

MISO

SS

T0

T1

CMP2

CIN2B

CIN2A

CMP1

CIN1A

CIN1B

OCA

OCB

OCC

OCD

ICA

ICB

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

002aae102

P89LPC9321_1

Product data sheet

Rev. 01 — 9 December 2008

© NXP B.V. 2008. All rights reserved.

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