tm TE
CH
T431616A
Page Write cycle at Different Bank @ Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
H IG H
CS
RAS
CAS
*N ote2
ADDR
RAa
CAa RBb
CBb
CAc
CBd
BA
A 10/A P
RAa
RBb
DQ
WE
DQM
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
tC D L
tR D L
*N ote1
R ow A ctive
(A -B ank)
R ow A ctive
(B -B ank)
W rite (A -
Bank)
W rite (B -
Bank)
W rite (A -
Bank)
W rite (B -
Bank)
Precharge
(A -B ank)
:D on't care
*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
Taiwan Memory Technology, Inc. reserves the right P.20
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C