tm TE
CH
T431616A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
H IG H
CS
RAS
tR C D
CAS
tC C D
* N o te2
ADDR
Ra
C a0
C b0
C c0
C d0
BA
A 10/A P
CL=2
DQ
CL=3
Q a0 Q a1 Qb0 Qb1 Qb2
Q a0 Q a1 Qb0 Q b1
tR D L
D c0 D c1 D d0 Dd1
tC D L
D c0 D c1 D d0 D d2
WE
DQM
* N o te1
* N o te3
R o w A ctiv e
(A -B nak)
R ead (A -
B nak)
R ead (A -
B nak)
W rite (A -
B nak)
W rite (A -
B nak)
P recharge
(A -B nak)
:D o n 't c a re
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
Taiwan Memory Technology, Inc. reserves the right P.18
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C