NT7502 Ver la hoja de datos (PDF) - Novatek Microelectronics

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Fabricante

NT7502

65 X 132 RAM-Map LCD Controller / Driver

Novatek Microelectronics 

NT7502

CS1

CS2

SI

SCL

A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2

12345

6

7

8

9 10 11 12 13 14

Figure. 1

# When the chip is not active, the shift registers and the counter are reset to their initial states.

# Reading is not possible while in serial interface mode.

# Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend the

operation be rechecked on the actual equipment.

Chip Select Inputs

The NT7502 has two chip select pads. CS1 and CS2 can interface to a microprocessor when CS1 is low and CS2 is high.

When these pads are set to any other combination, D0 to D7 are high impedance and A0, E and R / W inputs are disabled.

When serial input interface is selected. the shift register and counter are reset.

Access to Display Data RAM and Internal Registers

The NT7502 can perform a series of pipeline processing between LSI’s using the bus holder of the internal data bus in order to

match the operating frequency of display RAM and internal registers with the microprocessor. For example, the microprocessor

reads data from display RAM in the first read (dummy) cycle, stores it in the bus holder, and outputs it onto system bus in the

next data read cycle.

Also, the microprocessor temporarily stores display data in the bus holder, and stores it in display RAM until the next data write

cycle starts.

When viewed from the microprocessor, the NT7502 access speed greatly depends on the cycle time rather than access time to

the display RAM (tACC). This view shows the data transfer speed to / from the microprocessor can increase. If the cycle time is

inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a

restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the

immediately following read instruction. The address data is output during the second data read. A single dummy read must be

inserted after address setup and after the write cycle (refer to Figure2).

10

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