HEC4024BF Ver la hoja de datos (PDF) - Philips Electronics
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HEC4024BF Datasheet PDF : 5 Pages
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Philips Semiconductors
7-stage binary counter
DESCRIPTION
The HEF4024B is a 7-stage binary ripple counter with a
clock input (CP), and overriding asynchronous master
reset input (MR) and seven fully buffered parallel outputs
(O0 to O6). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of CP. Each
counter stage is a static toggle flip-flop.
Product specification
HEF4024B
MSI
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4024BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4024BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4024BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
PINNING
CP
MR
O0 to O6
clock input (HIGH to LOW triggered)
master reset input
buffered parallel outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4024B are:
• Frequency dividers
• Time delay circuits
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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