NJW4302 Ver la hoja de datos (PDF) - Japan Radio Corporation
Número de pieza
componentes Descripción
Fabricante
NJW4302 Datasheet PDF : 18 Pages
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NJW4302
s FUNCTIONAL DESCRIPTION
1. VCO circuit
Preliminary
The variable range of PLL circuit is determined by two factors: VCO frequency determined by RC value connected
to Pin 15 and Pin 16 and VCO loop filter constants. VCO frequency range must be within 160kHZ to 1.0MHZ.
The typical external value is as follows:
R=20kΩ,C=100pF.
The filter constants are C=0.47µF,R=27kΩ.
2. Output drive circuit
The PWM control is made by upper side of external transistor.
3. Speed lock range
The speed lock range is ±6.25% of fixed speed. When the motor speed is within the lock range, the LD pin
(an open collector output)goes “L”. If the motor speed goes out of the lock range, the LD pin goes “H”.
Please be noted that the LD signal may go on during startup.
4. PWM frequency
The PWM frequency is determined by resistor and capacitor value connected to the CR pin.
The PWM frequency is given by expressed as:
fPWM=1/(0.48CR)
When C=1500pF,R=75KΩ,the PWM frequency goes about 19KHz.
5. Lock detection circuit(CLOCK)
Lock detection circuit protects the driver IC and the motor from fatal over current failure when the motor is
locked during startup. If the LD output remains “H” (motor lock state) for a certain period (Hold time),all phase of upper
side transistors are to be turned off.
The hold time can be programmed by capacitor value attached to the CLOCK pin by the following:
Set time(sec) =66×C(µF)
With C=0.068µF,the hold time can be programmed for approximately 4.5 sec.
Once Lock detection circuit is activated, the state remains unchanged unless it is turned off, or stopped.
This function can be disabled when the CLOCK pin is connected to the ground.
6. Forward / Reverse(F/R)Switching
The direction control can be made with the state of the F/R pin. The direction can be changed even during the
motor in motion.
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