NJU6679 Ver la hoja de datos (PDF) - Japan Radio Corporation
Número de pieza
componentes Descripción
Fabricante
NJU6679 Datasheet PDF : 46 Pages
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NJU6679
TERMINAL DESCRIPTION
No.
1,40
5,22
39
38
37
36
35
Symbol I/O
Function
VDD
Power VDD=+3V
VSS
GND VSS=0V
V1
Power LCD Driving Voltage Supplying Terminal. When the internal voltage booster is
V2
not used, supply each level of LCD driving voltage from outside with following
V3
relation.
V4
VDD>V1>V2>V3>V4>V5
V5
When the internal power supply is on, the internal circuits generate and supply
following LCD bias voltage from V1 to V4 terminals.
Bias
1/4Bias
1/5Bias
1/6Bias
1/7Bias
1/8Bias
1/9Bias
1/10Bias
1/11Bias
1/12Bias
V1
V2
V3
V4
V5+3/4VLCD V5+2/4VLCD V5+2/4VLCD V5+1/4VLCD
V5+4/5VLCD V5+3/5VLCD V5+2/5VLCD V5+1/5VLCD
V5+5/6VLCD V5+4/6VLCD V5+2/6VLCD V5+1/6VLCD
V5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5+1/7VLCD
V5+7/8VLCD V5+6/8VLCD V5+2/8VLCD V5+1/8VLCD
V5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5+1/9VLCD
V5+9/10VLCD V5+8/10VLCD V5+2/10VLCD V5+1/10VLCD
V5+10/11VLCD V5+9/11VLCD V5+2/11VLCD V5+1/11VLCD
V5+11/12VLCD V5+10/12VLCD V5+2/12VLCD V5+1/12VLCD
33,32,
31,30,
29,28,
27,26,
25,24
23
34
7
6
C1+,C1-
C2+,C2-
C3+,C3-
C4+,C4-
C5+,C5-
VOUT
VR
T1
T2
(VLCD=VDD-V5)
O Step up capacitor connecting terminals.
Voltage booster circuit (Maximum 6-time)
O Step up voltage output terminal. Connect the step up capacitor between this
terminal and VSS.
I Voltage adjust terminal. V5 level is adjusted by external bleeder resistance
connecting between VDD and V5 terminal.
I LCD bias voltage control terminals. ( *:Don't Care)
T1
T2
V o lta g e
b o o s te r C ir.
V o lta g e A d j.
V /F C ir.
L
*
A v a ila b le
A v a ila b le
A v a ila b le
H
L
N o t A v a il.
A v a ila b le
A v a ila b le
H
H
N o t A v a il.
N o t A v a il.
A v a ila b le
14 to 21
11
D0 to
D7
(SI)
(SCL)
A0
I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.
P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input
terminal. Data from SI is loaded at the rising edge of SCL and
latched as the parallel data at 8th rising edge of SCL.
I Connect to the Address bus of MPU. The data on the D 0 to D7 is
distinguished between Display data and Instruction by status of A0.
A0
H
L
Distin. Display Data Instruction
4
RES
I Reset terminal. When the RES terminal goes to "L", the initialization is
performed. Reset operation is executing during "L" state of RES.
10
CS
I Chip select terminal. Data Input/Output are available during CS ="L".
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